1. Field of the Invention
This invention relates generally to floating gate memory devices such as an array of flash electrically erasable programmable read-only memory (EEPROM) cells. More particularly, the present invention relates to an improved drain power supply for generating and supplying a regulated positive potential to drain regions of selected memory cells via bit lines in an array of flash EEPROM memory cells during programming.
2. Description of the Prior Art
In U.S. Pat. No. 5,077,691 to Sameer S. Haddad et al. issued on Dec. 31, 1991, there is disclosed a flash EEPROM array which includes a positive drain voltage charge pump 201. The '691 patent is assigned to the same assignee as in the present invention and is hereby incorporated by reference. During a sector-programming mode of operation, the charge pump 201 of FIG. 2B of the '691 patent generates a high level positive potential (i.e., +6 V) which is applied to the drain regions via the bit lines of the selected sectors while the drain regions of the memory cells in the non-selected sectors are floating. Further, the control gates of all transistors in the selected sectors are raised into a relatively high positive voltage of approximately +12 volts, and the source regions thereof are pulled to a ground potential of zero volts. In FIG. 5C of the '691 patent, there is shown a schematic of a charge pump circuit having a single positive voltage charge pump stage 502 for generating +6 volts. The charge pump circuit of FIG. 5C is used for the charge pump block 201 shown in FIG. 2B of the '691 patent.
In U.S. Pat. No. 5,126,808 to Antonio J. Montalvo et al. issued on Jun. 30, 1992, there is disclosed a flash EEPROM array with paged erase architecture which also includes a positive drain voltage charge pump. The '808 patent is also assigned to the same assignee as in the present invention and is hereby incorporated by reference. In FIG. 7F of the '808 patent, there is shown a schematic of a charge pump circuit 576 formed of a single positive voltage charge pump stage 570, similar to FIG. 5C of the '691 patent, for generating the high level positive potential of approximately +6 volts.
The present invention represents a significant improvement over the charge pump circuits shown in the respective '691 and '808 patents discussed above. The drain power supply of the present invention is used for generating and supplying a regulated positive potential to drain regions of selected memory cells via bit lines in an array of flash EEPROM memory cells during programming. The present drain power supply has been designed to supply approximately 6 mA and can be regulated between +6.5 V and +6.9 V over the military temperature and power supply ranges.
The drain power supply includes a positive charge pump circuit formed of a plurality of charge pump sections each being driven by one of a plurality of staggered clock signals for generating a moderately high level positive voltage. A cancellation circuit is coupled to each of the plurality of charge pump sections for effectively canceling out threshold voltage drops in the charge pump circuit. The drain power supply further includes a regulation circuit which is responsive to the regulated positive potential at an output node and a reference voltage for generating a control voltage which is varied increasingly so as to reduce the high level positive voltage to the output node and which is varied decreasingly so as to increase the high level positive voltage to the output node. The drain power supply of the present invention has increased pump efficiency, reduction of VCC and VSS noise, ripple reduction, and lower power dissipation than those power supplies traditionally available.